1. Field of the Invention
The present invention relates generally to a fuse latch circuit that latches a fuse state during a power-on initialization time period, and more particularly to a fuse latch circuit to be used with a redundancy-functionality-containing memory or a redundancy-functionality-containing memory embedded microcomputer, for which stable operation, low current consumption, and chip size reduction are demanded.
2. Description of Related Art
FIG. 1 shows an example of a conventional fuse latch circuit. FIG. 2 shows an example system using fuse latch circuits, one of which is shown in FIG. 1.
A fuse latch circuit group 110 is configured of 240 fuse latch circuits L0, L1, . . . , L239. An internal circuit 12 outputs respective control signals CNT0, CNT1, . . . , CNT239 in accordance with respective output signals FUSEOT0, FUSEOT1, . . . , FUSEOT239 of the fuse latch circuits L0, L1, . . . , L239.
Each fuse latch circuit Ln (where n=0, 1, . . . , 239) is configured of high “on” resistance p-channel MOS transistors P1 and P2, inverters INV1 and INV2, a resistor R, a fuse (such as an aluminum fuse) AL-fuse, and capacitors C1 and C2.
The capacitor C1 has the function of setting a node Va to a power supply level (VDD) at the power-on time. The capacitor C2 has the function of setting a node Vb to a ground level (VSS) at the power-on time. However, during system initialization, the node Va becomes the ground level, and the node Vb becomes the power supply level.
Other example fuse latch circuits are disclosed in, for example, Jpn. Pat. Appln. KOKAI Publications No. 2002-298594, No. 2000-311496, No. 2002-175696, No. 05-41096, and No. 2002-093188.
Fuse Connection Case
FIG. 3 shows operation of the fuse latch circuit shown in FIG. 1 in a fuse connection case (non-disconnection case).
First, in a time T1 or immediately before the system initialization, since a control signal INTV is set to an “H” level, the node Va becomes a ground level (“L” level). At this time, also the output signal FUSEOTn of the fuse latch circuit Ln becomes the “L” level.
At a system initialization time T2, since the control signal INTV becomes the “L” level, the p-channel MOS transistor P1 is set to an ON state. Consequently, the node Va enters a precharge state, and a current path occurs in the route “power supply→transistor P1→node Va→resistor R→fuse AL-fuse→ground point.”
A let-through current in units of one fuse latch circuit in the above-described state is about 25 μA. However, assumptions are made that the power supply level (VDD) is about 3.3 V, and the temperature is normal temperature.
The system shown in FIG. 2 has the 240 fuse latch circuits L0, L1, . . . , L239. Individual operation timings of the fuse latch circuits L0, L1, . . . , L239 are identical to one another, so that a let-through current ivdd of about 6 mA in total flows across the overall system.
Consequently, the let-through current ivdd arises the probability of a power-supply potential fall. In addition, power consumption in a memory or a memory embedded microcomputer employed by the system is increased.
Further, to prevent potential variations in the node Va due to the let-through current ivdd, such a manner as to set a circuit threshold value of an inverter INV1 is frequently practiced. In this case, however, if the circuit threshold value of the inverter INV1 increases to the power supply level, a failure mode takes place. More specifically, the output signal FUSEOTn is set to “L” while it inherently is to be “H” in the system initialization time T2.
Fuse Disconnection Case
FIG. 4 shows operation of the fuse latch circuit shown in FIG. 1 in a fuse connection case.
First, in the time T1 or immediately before the system initialization, since the control signal INTV is set to an “H” level, the node Va becomes the ground level (“L” level). At this time, also the output signal FUSEOTn of the fuse latch circuit Ln becomes the “L” level.
At the system initialization time T2, since the control signal INTV becomes the “L” level, the p-channel MOS transistor P1 is changed to the ON state. Consequently, the node Va enters a precharge state. Precharge of the node Va requires a sufficiently long precharge time in association with the capacitance (=large) of the capacitor C1 and a conductance gmA (=high) of the high “on” resistance p-channel MOS transistor P1.
For the reason described above, when, for example, a pulse width of the control signal INTV, i.e., the time T2, is excessively short, the potential of the node Va is unable to reach a predetermined precharge level. As a consequence, a failure mode takes place in which the potential of the node Va remains unable to exceed the circuit threshold value of the inverter INV1, and the output signals FUSEOTn that should inherently becomes “H” changes to “L.”
In addition, for example, when the pulse width of the control signal INTV varies, the redundancy functionality is disabled in a state where the pulse width is narrow. Consequently, faulty data is transferred to a system bus to be used as data such as instruction data or control data, so that a system failure is induced.
FIG. 5 shows an example layout for five units of the fuse latch circuits shown in FIG. 1.
Fuses AL-fuse are formed in a fuse area. In a transistor area, p-channel MOS transistors P1 and P2 and inverters INV1 and INV2 are formed in a transistor area. Wirelines W1, W2, and W3 are formed in a wireline area; resistors R are formed in a resistor area; and capacitors C1 and C2 are formed in a capacitor area.
The size necessary for one of the fuse circuits is about 588 μm2 (i.e., about 73.2 μm×about 8.04 μm=about 588 μm2). Therefore, in the system shown in FIG. 2 having 240 fuse latch circuits, the area required for the fuse latch circuit group is about 141,247 μm2 (i.e., about 73.2 μm×about 8.04 μm×240 units=about 141,247 μm2).
In recent years, there is the tendency of using an increased number of fuse latch circuits in one system, consequently increasing the ratio in the occupation area of a fuse latch circuit group in a memory-macro control circuit. Consequently, the chip size is increased in, for example, a memory or memory embedded microcomputer in which the system is mounted.
Accordingly, for an integrated circuit such as a memory or memory embedded microcomputer having fuse latch circuits, it is important to implement system stabilization and low current consumption by eliminating let-through current during the initial operation time. In addition, it is important to arrange the configuration not causing erroneous operation even when the pulse width of the control signal for initializing the system is narrow and to reduce the layout area of the fuse latch circuits.